1. Field of the Invention
Embodiments of the present invention relate to a semiconductor device.
2. Background
Traditionally, inverters for industrial application have been using transformers and photo-couplers to perform electrically isolated signal transmission in the gate driving of switching elements such as insulated gate bipolar transistors (IGBTs) that compose a power conversion bridge circuit. Recently, however, the transformers and photo-couplers are replaced for cost reduction in low capacity applications, in particular, by high voltage integrate circuits (HVICs) that do not perform electrical insulation. U.S. Patent Application Publication No. 2006/0220168, M. Yoshino et al., “A new 1200 V HVIC with a novel high voltage Pch-MOS”, Proceedings of the 22nd International Symposium on Power Semiconductor Devices & ICs, Hiroshima, 2010, pp. 93-96, (“Yoshino et al. '2010”) and M. Yoshino et al., “A novel high voltage new Pch-MOS with a new drain drift structure for 1200 V HVICs”, Proceedings of the 25th International Symposium on Power Semiconductor Devices & ICs, Kanazawa, 2013, pp. 77-80, (“Yoshino et al. '2013”), for example, disclose such HVICs. The following describes the construction of a conventional HVIC.
FIG. 15 is a plan view showing the overall construction of a conventional HVIC. FIG. 16 is a circuit diagram showing the circuit construction of the HVIC depicted in FIG. 15. The following describes an example of HVIC 100 connected to a bridge circuit 120 of a power converter and driving the first IGBT 121 at the high side of the first and second IGBTs 121 and 122 composing one phase of the bridge circuit 120 of a power converter. The conventional HVIC 100 shown in FIG. 15 and FIG. 16 includes, on a single semiconductor chip, a high side gate driving circuit 101, and abnormality detecting circuit 102, an input/control circuit 103, a level shift-up circuit 104, a level shift-down circuit 107, and a high voltage junction terminating (HVJT) structure 111.
The high side gate driving circuit 101 and the abnormality detecting circuit 102 are disposed in the high side well region 112 and is operated with a reference potential of the emitter potential VS of the first IGBT 121 at the high side of the bridge circuit 120 of a power converter, a power supply potential of VB, and a power supply voltage of VCC′. The high side well region 112 is a high voltage region having a floating potential electrically isolated from the low side region 113 by the high voltage junction terminating structure 111. The abnormality detecting circuit 102 transmits an abnormality signal to the input/control circuit 103. The VB potential is a sum of a power supply voltage VCC′ and the emitter potential VS of the first IGBT 121 at the high side of the bridge circuit 120 of the power converter: VB=VS+VCC′.
The input/control circuit 103 is located in the low side region 113 and operates with a reference potential of GND potential. The input/control circuit 103 is operated with a power supply potential VCC supplied from the VCC terminal and controls the output HO of the high side gate driving circuit 101 according to a control signal HIN from an external microcontroller, for example, and an abnormality detection signal from the abnormality detecting circuit 102. The level shift-up circuit 104 is composed of two level shift circuits for a setting signal and for a resetting signal. Each of the two level shift circuits is composed of an n channel metal oxide semiconductor field effect transistor (nch MOSFET) 105 with a high breakdown voltage and a level shift resistor 106.
The nch MOSFET 105 of the level shift-up circuit 104 is disposed in the high voltage junction terminating structure 111, and the level shift resistor 106 is disposed in the high side well region 112. The level shift-up circuit 104 converts the setting signal and resetting signal with the reference potential of the ground potential fed from the input/control circuit 103 into signals with a reference potential of the VB potential, and delivers the converted signals to a latching circuit 110 at the next stage. The set signal is given to turn ON the high side gate driving circuit 101 for delivering a gate signal HO to the first IGBT 121 at the high side of the bridge circuit 120 of the power converter. The reset signal is given to turn OFF the high side gate driving circuit 101.
The output terminal Q of the latching circuit 110 is connected to the gate terminal of a p channel MOSFET (pch MOSFET) for charging the gate of the first IGBT 121 at the high side of the bridge circuit 120 of the power converter and to the gate terminal of an nch MOSFET for discharging the gate of the first IGBT 121. The level shift-down circuit 107 is composed of a high voltage pch MOSFET 108 and a level shift resistor 109. The pch MOSFET 108 of the level shift-down circuit 107 is disposed in the high voltage junction terminating structure 111 and the level shift resistor 109 is disposed in the low side region 113. The level shift-down circuit 107 transforms an abnormality detection signal with a reference potential of VB potential delivered from the abnormality detecting circuit 102 into a signal with a reference potential of the ground potential, and transmits the signal into the input/control circuit 103. FIG. 16 also indicates a bootstrap diode 124 and a bootstrap capacitor 125.
A planar construction of the high side well region 112 and the surroundings thereof of the conventional HVIC 100 is described below. FIG. 17 is a plan view showing in detail the planar construction around the high side well region of the HVIC of FIG. 15. FIG. 17 shows only one nch MOSFET 105 of the level shift-up circuit 104 to clearly show the planar construction of the conventional HVIC 100. As shown in FIG. 17, the high side well region 112 is composed of an n type diffusion region 14 and a low concentration n− type diffusion region 13 surrounding the n type diffusion region 14. The n− type diffusion region 13 and the n type diffusion region 14 are connected to the VB potential. The n− type diffusion region 13 is surrounded by the n− type diffusion region 1.
Between the n− type diffusion region 13 and the n− type diffusion region 1, a p− diffusion region 12, which is an isolating region, is provided. The n− type diffusion region 1 is surrounded by a p+ type diffusion region 11 at a GND potential, which is a p+ type GND region. In the n type diffusion region 14 arranged are a high side gate driving circuit 101, the abnormality detecting circuit 102, and the components of the level shift-up circuit 104 including the level shift resistor 106 but excluding the nch MOSFET 105. In the n− type diffusion region 1 arranged are the high voltage junction terminating structure 111, the nch MOSFET 105 of the level shift-up circuit 104, and the pch MOSFET 108 of the level shift-down circuit 107.
The following describes the sectional construction of the nch MOSFET 105, the pch MOSFET 108, and the high voltage junction terminating structure 111 of the conventional HVIC 100. FIG. 18 is a sectional view showing the sectional construction along the line AA-AA′ indicated in FIG. 17; FIG. 19 is a sectional view showing the sectional construction along the line BB-BB′ indicated in FIG. 17; and FIG. 20 is a sectional view showing the sectional construction along the line CC-CC′ indicated in FIG. 17. FIG. 18 depicts the sectional construction of the nch MOSFET 105; FIG. 19 depicts the sectional construction of the pch MOSFET 108; and FIG. 20 depicts the sectional construction of the high voltage junction terminating structure 111.
Commonly in the sectional constructions of FIGS. 18, 19 and 20 shown are the n− type diffusion region 1, and n− type diffusion region 13 and the n type diffusion region 14 composing the high side well region 112 selectively formed in the front surface region of the p type semiconductor substrate 10. The n− type diffusion region 13 is disposed in the outer peripheral side than the n type diffusion region 14, and the n− type diffusion region 1 is disposed in the outer peripheral side than the high side well region 112. A p− type diffusion region 15 is provided in the outer peripheral side of the substrate on the front surface layer of the substrate. The p− type diffusion region 15 penetrates in the depth direction through the n− type diffusion region 1 reaching a p type region in the back surface side of the substrate. In the p− type diffusion region 15, a p+ type GND region 11 is selectively provided.
As shown in FIG. 18, the nch MOSFET 105 of the level shift-up circuit 104 is provided with a RESURF structure with the n− type diffusion region 1 and the p type semiconductor substrate 10, the RESURF structure being a single RESURF structure. The n− type diffusion region 1 also functions as a drift region. The impurity concentration of the n− type diffusion region 1 is about 1.0×1012/cm2. In the n− type diffusion region 1 around the nch MOSFET 105, an isolation region 12 is provide between the n− type diffusion region 1 and the n− type diffusion region 13 in the deeper depth than the n− type diffusion region 1 from the front surface of the substrate. The isolation region 12 isolates the n− type diffusion region 1 from the n− type diffusion region 13.
M. Imam et al., “Design and Optimization of Double-RESURF High-Voltage Lateral Devices for a Manufacturable Process”, IEEE Transactions on Electron Devices, vol. 50, no. 7, July 2003, pp, 1697-1701, (“Imam et al.”) for example, discloses that the optimum impurity concentration of an n− type diffusion region 1 is at most 1.4×1012/cm2 to obtain a desired breakdown voltage for a single RESURF structure.
As shown in FIG. 19, the pch MOSFET 108 of the level shift-down circuit 107 has a double RESURF structure with a p type diffusion region 2, the n− type diffusion region 1, and the p type semiconductor substrate 10. In the n− type diffusion region 1 around the pch MOSFET 108, the isolation region 12 is not provided between the n− type diffusion region 1 and the n− type diffusion region 13, and the n− type diffusion region 1 is in contact with the n−type diffusion region 13. The p type diffusion region 2 is formed in the front surface layer of the substrate with a depth shallower than the n− type diffusion region 1. The p type diffusion region 2 not only composes a double-RESURF structure, but also functions as a p type drift region. The impurity concentration of the p type diffusion region 2 is in the range of 5.0×1011/cm2 to 1.0×1012/cm2.
As shown in FIG. 20, the high voltage junction terminating structure 111 has, like the nch MOSFET 105, a single RESURF structure with the n− type diffusion region 1 and the p type semiconductor substrate 10. In the place of the high voltage junction terminating structure 111, the isolation region 12 is provided between the n− type diffusion region 1 and the n− type diffusion region 13, and the n− type diffusion region 1 is isolated from the n− type diffusion region 13 by the isolation region 12.
In FIG. 18, the symbols 3, 4, 5, 7, 8, and 9 represent the components composing a structure of MOS gate structure, which is an insulated gate structure comprising a metal-oxide film-semiconductor gate, of the nch MOSFET 105. The symbol 16 in FIG. 18 indicates a contact, which is an electrical contact region, between a VB electrode 39 and the n type diffusion region 14. The symbols 24, 25, 27, 28, and 29 (in FIG. 19) represent the components composing the MOS gate structure of the pch MOSFET 108. The symbols 31, 32 and 33 (in FIGS. 18, 19, and 20) represent local oxidation of silicon film (LOCOS film), interlayer dielectric film, and a resistive field plate, which is a resistor functioning as a field plate, respectively. The symbols 34 and 35 (in FIG. 18) represent a source electrode and a drain electrode of the nch MOSFET 105, respectively. The symbols 36 and 37 (in FIG. 19) represent a source electrode and a drain electrode of the pch MOSFET 108. The symbols 38 (in FIG. 19) and 40 (in FIG. 18) represent a GND electrode and a field plate, respectively.
Now, operation of the conventional HVIC 100 will be described below. A control signal from a microcontroller, for example, given to the input/control circuit 103 is transmitted to the high side gate driving circuit 101 to drive the first IGBT 121 at the high side, for example, connected to the conventional HVIC 100, of the first IGBT 121 and the second IGBT 122 composing one phase of the bridge circuit 120 of a power converter. When the abnormality detecting circuit 102 detects any abnormality such as over-current or over-heating, the abnormality detecting circuit 102 transmits an abnormality signal to the input/control circuit 103, and the first IGBT 121 at the high side is turned OFF and the abnormality is notified to the microcontroller.
As described earlier, the high side gate driving circuit 101 is operated on a reference potential of the emitter potential VS of the first IGBT 121 at the high side of the bridge-connected circuit, wherein the potential VS is the potential at the node 123 between the first IGBT 121 and the second IGBT 122 at the low side. The reference potential of the high side gate driving circuit 101 rises to several hundred volts at the maximum above the reference potential, which is the ground potential, of the input/control circuit 103. However, the high voltage junction terminating structure 111 holds a breakdown voltage between the high side gate driving circuit 101 and the input/control circuit 103.
Japanese Patent No. 3952967 discloses a HVIC of this type. This HVIC has a three layer structure comprising a first region of a first conductivity type, a second region of a second conductivity type formed selectively in the surface layer of the first principal surface of the first region, and a third region of the first conductivity type formed selectively in the surface layer of the second region. The net doping amount of the second region is in the range of 1×1011/cm2 to 4×1012/cm2 so that the depletion layer extending to both sides of a first pn junction between the first region and the second region and the depletion layer extending to both sides of a second pn junction between the second region and the third region are united in the second region, when both the first pn junction and the second pn junction are reversely biased. The net doping amount of the third region is in the range of 1×1011/cm2 to 2×1012/cm2 so that the depletion layer extending to both sides of the second pn junction reaches the surface of the third region. The HVIC further includes, inside an area surrounded by the third region, a second conductivity type region electrically connected to the second region, a first conductivity type region selectively formed in the surface layer of the second conductivity type region, a first conductivity type channel MIS transistor formed in the surface layer of the second conductivity type region, and a second conductivity type channel MIS transistor formed in the surface layer of the first conductivity type region.
Japanese Patent No. 3214818 discloses another HVIC. This HVIC includes: a semiconductor material layer of a first conductivity type disposed on a semiconductor substrate and having an upper surface subjected to doping treatment, a base region of a second conductivity type formed in the surface region of the semiconductor material layer to a predetermined depth and having substantially a semicircular shape, a source region of the first conductivity type formed in the base region and forming a surface channel region between the source region and the semiconductor material layer, a source electrode in contact with the source region and electrically connected to a low voltage reference control circuit, a gate insulating layer disposed so as to be in contact with the source region and a part of the upper surface of the surface channel region, a conductive gate layer disposed in the gate insulating layer, a drain region formed in the upper surface region of the semiconductor material layer at a position laterally apart from the base region, a drain electrode formed on the drain region and in contact with a part of the upper surface of the semiconductor material layer, a contact electrode in contact with another part of the upper surface of the semiconductor material layer and electrically connected to a floating high voltage circuit, in which a part of the semiconductor material layer at the position between the contact electrode and the drain electrode forms a conductive region, and a resistance element disposed between the drain electrode and the contact electrode and arranged electrically in parallel to the conductive region of the semiconductor material layer. The base region with a substantially semicircular shape forms a peripheral ring part of the floating high voltage circuit, and a level shift circuit is provided in the peripheral ring part.
Japanese Unexamined Patent Application Publication No. H09-055498 discloses still another HVIC. The HVIC includes: a first region of a p type semiconductor substrate, an n type second region selectively formed in the surface layer of the first region, a p type third region selectively formed in the surface layer of the second region, an n type fifth region selectively formed in the surface layer of the second region, a p type sixth region selectively formed in the surface layer of the third region, a pch MOSFET formed in the surface layer of the second region, an nch MOSFET formed in the surface layer of the third region, and a high voltage junction terminating structure provided surrounding the first region.
However, the conventional HVIC 100 described above referring to FIG. 15 and FIG. 16 has the following problems. As described earlier, the conventional HVIC 100 employs a single RESURF structure in the nch MOSFET 105 and in the high voltage junction terminating structure 111 composed of the n− type diffusion layer 1 and the p type semiconductor substrate 10, whereas the pch MOSFET 108 employs a double RESURF structure composed of the p type diffusion region 2, the n− type diffusion region 1, and the p type semiconductor substrate 10. As a result, the optimum condition for the n− type diffusion region 1 differs for the pch MOSFET 108, and for the nch MOSFET 105 and the high voltage junction terminating structure 111.
More specifically, as described in Imam et al., the optimum impurity concentration of the n− type diffusion region 1 to obtain a desired breakdown voltage is at most 1.4×1012/cm2 for a single RESURF structure. An impurity concentration higher than this value cannot ensure sufficient breakdown voltage. For the double RESURF structure, the optimum impurity concentration of the n− type diffusion region 1 to ensure the breakdown voltage between the p type diffusion region 2 and the n− type diffusion region 1 is at most 2.8×1012/cm2. In order to ensure a desired breakdown voltage, an impurity concentration of the p type diffusion region is at most 1.4×1012/m2 and at the same time it is necessary that the difference between the impurity concentrations in the p type diffusion region 2 and in the n− type diffusion region 1 is at most 1.4×1012/cm2. These conditions for the impurity concentration of the p type diffusion region 2 is necessary conditions to obtain a desired breakdown voltage and not a sufficient condition. To obtain a desired breakdown voltage, optimization is needed to the impurity concentration of the p type diffusion region 2 while satisfying the above-mentioned necessary conditions. The optimum impurity concentration of the p type diffusion region 2 depends on the impurity concentration of the n− type diffusion region 1; a low impurity concentration for the n− type diffusion region 1 leads to lower optimum impurity concentration of the p type diffusion region 2.
A lower impurity concentration of the n− type diffusion region 1 tends to lower the optimum impurity concentration of the p type diffusion region 2 because the amount of positive space charges in the depletion layer has to be balanced with the amount of negative space charges. Therefore, a low impurity concentration of the n− type diffusion region 1 means a small amount of positive space charges, which are donors, in the n− type diffusion region 1, reducing the negative space charges, which are acceptors, allowed in the depletion layer of the p type diffusion region 2. When the impurity concentration in the p type diffusion region 2 is higher than the impurity concentration of the n− type diffusion region 1, deficiency of the positive space charges causes incomplete depletion of the p type diffusion region 2, resulting in insufficient breakdown voltage.
Negative space charges in a depletion layer exist not only in the depletion layer extending from pn junction between the p type diffusion region 2 and the n− diffusion region 1 into the p type diffusion region 2, but also exist in an approximately same amount in the depletion layer extending from the pn junction between the p type semiconductor substrate and the n− type diffusion region 1 into the p type semiconductor substrate. Consequently, in order to make the p type diffusion region 2 thoroughly depleted, the amount of the positive space charges in the n− type diffusion region 1 has to be about twice the amount of the negative space charges in the p type diffusion region 2. Therefore, the optimum impurity concentration in the p type diffusion region 2 for ensuring a sufficient breakdown voltage is about half the impurity concentration in the n− type diffusion region 1.
For this reason, a design condition to ensure a sufficient breakdown voltage in the nch MOSFET 105 and the high voltage junction terminating structure 111 with a single RESURF structure, a single RESURF condition, is that an impurity concentration Nd per unit area of the n− diffusion region 1 (hereinafter referred to simply as an impurity concentration of the n− diffusion region 1) is at most 1.4×1012/cm2, or the inequality Nd≦1.4×1012/cm2 holds. A double RESURF condition for the pch MOSFET 108 with a double RESURF structure to ensure a sufficient breakdown voltage is to satisfy the following four conditions.
The first condition is that the impurity concentration Nd of the n− type diffusion region 1 is about twice the impurity concentration Na of the p type diffusion region 2, or Nd≈2×Na. The second condition is that the impurity concentration Na of the p type diffusion region 2 is at most 1.4×1012/cm2 (Na≦1.4×1012/cm2). The third condition is that the impurity concentration Nd of the n− type diffusion region 1 is at most 2.8×1012/cm2 (Nd≦2.8×1012/cm2). The fourth condition is that the difference between the impurity concentration Nd of the n− type diffusion region 1 and the impurity concentration Na of the p type diffusion region 2 is at most 1.4×1012/cm2 (Nd−Na≦1.4×1012/cm2).
As a consequence, in a conventional HVIC 100, the condition for ensure a sufficient breakdown voltage is to satisfy both the single RESURF condition and the double RESURF condition. More specifically, both the single RESURF condition and the double RESURF condition are satisfied when the following two conditions are satisfied: firstly, the impurity concentration Nd of the n− type diffusion region 1 is at most 1.4×1012/cm2 (Nd≦1.4×1012/cm2); secondly, the impurity concentration Na of the p type diffusion region 2 is at most 7.0×10/cm2 (Na≦7.0×1011/cm2).
In order for the nch MOSFET 105 and the high voltage junction terminating structure 111 with a single RESURF structure to have a sufficient breakdown voltage, the impurity concentration Nd of the n− type diffusion region 1 needs to be at most 1.4×1012/cm2. The impurity concentration Na of the p type diffusion region 2 is necessarily at most 7.0×1011/cm2. When the impurity concentration Na of the p type diffusion region 2 is at a value approximately 7.0×1011/cm2, the pch MOSFET 108 cannot have a sufficient current carrying capacity because of the problems of a high drift resistance in the p type diffusion region 2 and the pinch-off of the p type diffusion region 2.
On the other hand, if the impurity concentration Na of the p type diffusion region 2 is raised in order for the pch MOSFET 108 with a double RESURF structure to exhibit sufficiently high current carrying capacity, the pch MOSFET 108 cannot have a sufficiently high breakdown voltage. In short, the conventional HVIC 100 is hardly provide optimum condition for both the current carrying capacity and breakdown voltage of the pch MOSFET 108. When the impurity concentration Nd of the n− type diffusion region 1 is a low value of about 1.0×1012/cm2, at the pn junction between the n− type diffusion region 1 and the p type diffusion region 2, an electric field is generated in the direction from the p type diffusion region 2 toward the p type semiconductor substrate 10, creating a leakage current to the p type semiconductor substrate 10. Thus, a breakdown voltage is hardly ensured between the p type diffusion region 2 and the p type semiconductor substrate 10.
As described later, in order to ensure a breakdown voltage between the p type diffusion region 2 and the p type semiconductor substrate 10, the impurity concentration Nd of the n− type diffusion region 1 in the pch MOSFET 108 should be at least 1.3×1012/cm2. Because a p type diffusion region 2 is formed on the surface of the n− type diffusion region 1 of the pch MOSFET 108, the impurity concentration of the n− type diffusion region 1 of the pch MOSFET, when formed by ion implantation homogeneous over the surface as usual, becomes lower than those of the n− diffusion regions 1 of the nch MOSFET 105 and the high voltage junction terminating structure 111. As commonly employed, when a diffusion depth of the p type diffusion region 2 is in the range of 1 μm to 2 μm, and the diffusion depth of the n− type diffusion region 1 is in the range of 10 μm to 30 μm, the impurity concentration of the n− type diffusion region 1 of the pch MOSFET 108 is lower by more than 10% than the impurity concentration of the nch MOSFET 105 and the n− type diffusion region 1 of the high voltage junction terminating structure 111.
As a consequence, even when the impurity concentration of the n− type diffusion region 1 of the nch MOSFET 105 and the impurity concentration of the n− type diffusion reign 1 of the high voltage junction terminating structure 111 are set at the upper limit value of 1.4×1012/cm2, the impurity concentration of the n− type diffusion region 1 of the pch MOSFET 108 becomes lower than 1.3×1012/cm2. Therefore, in order to adjust the impurity concentrations of the n− type diffusion regions 1 of the pch MOSFET 108, the nch MOSFET 105, and the high voltage junction terminating structure 111 to be a value of at least 1.3×1012/cm2 and at most 1.4×1012/cm2, which is required by the double RESURF condition, the ion implantation processes are carried out separately for the n− type diffusion region 1 for the pch MOSFET 108, and for the nch MOSFET 105 and the high voltage junction terminating structure 111. This causes increased process cost.
Yoshino et al. '2010 discloses a method of increasing the impurity concentration of the p type diffusion region 2 keeping a sufficient breakdown voltage to ensure a high current carrying capacity of the pch MOSFET 108 while maintaining the high breakdown voltage. This is achieved by a p type diffusion region 2 in a configuration of stripes for easy depletion. This method of the Yoshino et al. '2010, however, decreases the area of the drift region of p type diffusion region 2. Accordingly, in order to ensure a required current carrying capacity, the channel width of the pch MOSFET 108 needs to be sufficiently large, wherein the channel width is a width, in the direction perpendicular to the direction from a p+ type drain region 27 to the source region, of the channel, or a p type inversion layer generated in the n− diffusion region 1 at the place between a source region of a p type diffusion region 24 and a drift region of the p type diffusion region 2 in an ON state. The enlarged channel width of the pch MOSFET 108 causes a large parasitic capacitance of the pch MOSFET 108, which increases the displacement current associated with dV/dt surge voltage, which may cause malfunctioning of the HVIC.
Yoshino et al. '2013 discloses a method for ensuring a high breakdown voltage between the p type diffusion region 2 and the p type semiconductor substrate 10 in a structure having the p type diffusion region 2 of a stripe shape. However, Yoshino et al. '2013 fails to disclose a method for ensuring a high breakdown voltage between the p type diffusion region 2 and the p type semiconductor substrate 10 in a structure having the p type diffusion region 2 of a conventional structure without a stripe shape.